The present invention relates to a phase adjustment circuit and, more particularly, to a technique for discretely adjusting the phase relationship between a clock signal and a data signal in data communications.
In order to realize fast data transmission, it is necessary that data signals are input/output in synchronism with the clock signal. Particularly, where the frequency of the clock signal is over 100 MHz, it is necessary to use a PLL (Phase Locked Loop) or a DLL (Delay Locked Loop) to realize synchronization between the external clock signal to be supplied from outside the semiconductor integrated circuit and the internal clock signal to be used within the semiconductor integrated circuit.
FIG. 8 shows a configuration of a conventional phase adjustment circuit. The phase adjustment circuit is implemented as a digital DLL including a digital delay line 100 for delaying a clock signal CLK to produce a delayed clock signal Rclk, a phase comparator 101 for comparing the phase of the data signal Data with that of the delayed clock signal Rclk, and a delay control section 102 for controlling the amount of signal delay along the digital delay line 100 based on the comparison result from the phase comparator 101 (see, for example, Japanese Laid-Open Patent Publication No. 9-261018 and Japanese Laid-Open Patent Publication No. 11-88153).
A digital DLL is characteristic in that it is easy to design and the circuit scale thereof is relatively small. Therefore, using a digital DLL as the phase adjustment circuit, one can expect a reduction in the circuit area and power consumption, and the ease in design when there is a change of the process.
Typically, a digital delay line includes a plurality of delay units. By changing the number of delay units to be connected together in series, it is possible to adjust the gain of the digital delay line. In order to optimally adjust the timing between a data signal and a delayed clock signal, it is preferred that the amount of signal delay per delay unit, i.e., the delay resolution set along the digital delay line, is as small as possible with respect to the data rate. However, if the delay resolution of the digital delay line is excessively small, the phase adjusting speed may not be fast enough for variations in the phase of the data signal and that of the clock signal.
The phase adjusting speed is calculated as the delay resolution of the digital delay line multiplied by the number of times adjustment is done per unit time, which is the number of times the transition of the data signal and that of the clock signal are compared with each other by the phase comparator. Therefore, in a case where the data rate is low and the number of transitions per unit time is small, the phase adjusting speed may not be fast enough for the phase varying speed, whereby the data signal cannot properly be latched by the clock signal.
At present, there are various data transmission standards with different data rates. In order to optimize the performance of communications technology in conformity to one of the various data transmission standards, the gain of the digital delay line should be determined according to the data rate. Specifically, it is necessary to ensure a sufficient range over which the phase adjustment can be done while using a high phase adjustment resolution for fine adjustment in the case of a high data rate and using a lower phase adjustment resolution so as to suppress the circuit scale in the case of a low data rate.
However, as described above, the delay resolution (also referred to as the “minimum delay amount”) of the digital delay line is dictated by the delay amount per delay unit in the digital delay line, which is a fixed amount. Therefore, with the conventional phase adjustment circuit, it is difficult to optimally adjust the delay resolution according to the data rate.